* Grygorii Strashko <grygorii.strashko@xxxxxx> [180830 17:08]: > On 08/29/2018 07:47 PM, Tony Lindgren wrote: > > In general, it seems cpsw is just an interconnect instance > > (L4_FAST) with a control module (CPSW_WR) and a pile of > > independent other modules. That's described nicely in > > am437x TRM chapter "2.1.4 L4 Fast Peripheral Memory Map". > > So from that point of view the binding reg entries right > > now are all wrong :) > > TRM not consistent - for am5 it's one MMIO region. Well that same information is there in 57xx TRM in chapter "Table 26-1454. GMAC_SW Instance Summary". But yeah, all the cpsw internal devices are stuffed into a single interconnect target module. > > In the long run cpsw should be really treated as an > > interconnect instance with it's control module providing > > standard Linux framework services such as clock / > > regulator / phy / pinctrl / iio whatever for the other > > modules. > > > > Just my 2c based on looking at the interconnect, I'm > > not too familiar with cpsw otherwise. > > It's not separate modules. this is composite module which have only one > fck/ick and most of blocks can't even function without each other. > Above might be the case for Keystone 2, but not omap CPSW. > Keystone 2 - has packet processor, security accelerator, queue manager in > addition to its basic switch block. Yeah there's just one fck/ick as it's all in a single interconnect module. But you might want to look at the CPSW_WR device registers and see what gate clocks and other Linux generic subsystem services CPSW_WR could provide for the other cpsw internal devices. It might just make your life easier maintaining all these variants ;) Regards, Tony
