Re: [PATCH] drm/rockchip: vop: add rk3188 vop definitions

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在 2018/8/30 19:09, Heiko Stuebner 写道:
The rk3188 has 2 vops not using iommus which only output directly
to a rgb interface per vop. So all other output modes like hdmi
are provided by external brige chips.

Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
---
This depends on Sandy's + mine recent series enabling direct
rgb outputs of specific vops.

  .../display/rockchip/rockchip-vop.txt         |  1 +
  drivers/gpu/drm/rockchip/rockchip_vop_reg.c   | 89 +++++++++++++++++++
  drivers/gpu/drm/rockchip/rockchip_vop_reg.h   | 25 ++++++
  3 files changed, 115 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
index 502430d622f5..67cbb378f2b5 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt
@@ -11,6 +11,7 @@ Required properties:
          "rockchip,rk3126-vop";
          "rockchip,px30-vop-lit";
          "rockchip,px30-vop-big";
+        "rockchip,rk3188-vop";
          "rockchip,rk3288-vop";
          "rockchip,rk3368-vop";
          "rockchip,rk3366-vop";
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index c333ad35a081..b953965c249c 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -401,6 +401,93 @@ static const struct vop_data px30_vop_lit = {
      .win_size = ARRAY_SIZE(px30_vop_lit_win_data),
  };

+static const struct vop_scl_regs rk3188_win_scl = {
+    .scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
+    .scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
+    .scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
+    .scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
+};
+
+static const struct vop_win_phy rk3188_win0_data = {
+    .scl = &rk3188_win_scl,
+    .data_formats = formats_win_full,
+    .nformats = ARRAY_SIZE(formats_win_full),
+    .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0),
+    .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3),
+    .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15),
+    .act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0),
+    .dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0),
+    .dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0),
+    .yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0),
+    .uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0),
+    .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0),
+};
+
+static const struct vop_win_phy rk3188_win1_data = {
+    .data_formats = formats_win_lite,
+    .nformats = ARRAY_SIZE(formats_win_lite),
+    .enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1),
+    .format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6),
+    .rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19),
+    /* no act_info on window1 */
+    .dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0),
+    .dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0),
+    .yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0),
+    .yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16),
+};
+
+static const struct vop_modeset rk3188_modeset = {
+    .htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
+    .hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0),
+    .vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
+    .vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0),
+};
+
+static const struct vop_output rk3188_output = {
+    .pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
+};
+
+static const struct vop_common rk3188_common = {
+    .gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31),
+    .standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30),
+    .out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0),
+    .cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0),
+    .dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x3, 24),
+};
+
+static const struct vop_win_data rk3188_vop_win_data[] = {
+    { .base = 0x00, .phy = &rk3188_win0_data,
+      .type = DRM_PLANE_TYPE_PRIMARY },
+    { .base = 0x00, .phy = &rk3188_win1_data,
+      .type = DRM_PLANE_TYPE_CURSOR },
+};
+
+static const int rk3188_vop_intrs[] = {
+    0,
+    FS_INTR,
+    LINE_FLAG_INTR,
+    BUS_ERROR_INTR,
+};
+
+static const struct vop_intr rk3188_vop_intr = {
+    .intrs = rk3188_vop_intrs,
+    .nintrs = ARRAY_SIZE(rk3188_vop_intrs),
+    .line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12),
+    .status = VOP_REG(RK3188_INT_STATUS, 0xf, 0),
+    .enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4),
+    .clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8),
+};
+
+static const struct vop_data rk3188_vop = {
+    .intr = &rk3188_vop_intr,
+    .common = &rk3188_common,
+    .modeset = &rk3188_modeset,
+    .output = &rk3188_output,
+    .win = rk3188_vop_win_data,
+    .win_size = ARRAY_SIZE(rk3188_vop_win_data),
+    .feature = VOP_FEATURE_INTERNAL_RGB,
+};
+
  static const struct vop_scl_extension rk3288_win_full_scl_ext = {
      .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
      .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
@@ -771,6 +858,8 @@ static const struct of_device_id vop_driver_dt_match[] = {
        .data = &px30_vop_big },
      { .compatible = "rockchip,px30-vop-lit",
        .data = &px30_vop_lit },
+    { .compatible = "rockchip,rk3188-vop",
+      .data = &rk3188_vop },
      { .compatible = "rockchip,rk3288-vop",
        .data = &rk3288_vop },
      { .compatible = "rockchip,rk3368-vop",
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
index 7e9f2a02a808..c8396dc2706f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h
@@ -1011,4 +1011,29 @@
  #define PX30_GAMMA_LUT_ADDR            0x00a00
  /* px30 register definition end */

+/* rk3188 register definition */
+#define RK3188_SYS_CTRL            0x00
+#define RK3188_DSP_CTRL0        0x04
+#define RK3188_DSP_CTRL1        0x08
+#define RK3188_INT_STATUS        0x10
+#define RK3188_WIN0_YRGB_MST0        0x20
+#define RK3188_WIN0_CBR_MST0        0x24
+#define RK3188_WIN0_YRGB_MST1        0x28
+#define RK3188_WIN0_CBR_MST1        0x2c
+#define RK3188_WIN_VIR            0x30
+#define RK3188_WIN0_ACT_INFO        0x34
+#define RK3188_WIN0_DSP_INFO        0x38
+#define RK3188_WIN0_DSP_ST        0x3c
+#define RK3188_WIN0_SCL_FACTOR_YRGB    0x40
+#define RK3188_WIN0_SCL_FACTOR_CBR    0x44
+#define RK3188_WIN1_MST            0x4c
+#define RK3188_WIN1_DSP_INFO        0x50
+#define RK3188_WIN1_DSP_ST        0x54
+#define RK3188_DSP_HTOTAL_HS_END    0x6c
+#define RK3188_DSP_HACT_ST_END        0x70
+#define RK3188_DSP_VTOTAL_VS_END    0x74
+#define RK3188_DSP_VACT_ST_END        0x78
+#define RK3188_REG_CFG_DONE        0x90
+/* rk3188 register definition end */
+
  #endif /* _ROCKCHIP_VOP_REG_H */

Reviewed-by: Sandy Huang <hjc@xxxxxxxxxxxxxx>




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