Device tree binding of Memory Controller has been changed: GART has been
squashed into the MC, there are a new mandatory clock and #iommu-cells
properties.
Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
---
arch/arm/boot/dts/tegra20.dtsi | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 979f38293fe5..74f6e52291c5 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -617,16 +617,13 @@
mc: memory-controller@7000f000 {
compatible = "nvidia,tegra20-mc";
- reg = <0x7000f000 0x024
- 0x7000f03c 0x3c4>;
+ reg = <0x7000f000 0x400 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
+ clocks = <&tegra_car TEGRA20_CLK_MC>;
+ clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
- };
-
- iommu@7000f024 {
- compatible = "nvidia,tegra20-gart";
- reg = <0x7000f024 0x00000018 /* controller registers */
- 0x58000000 0x02000000>; /* GART aperture */
+ #iommu-cells = <0>;
};
memory-controller@7000f400 {
--
2.18.0
