On Mon, Jul 30, 2018 at 08:21:33PM -0700, Atish Patra wrote: > I found the issue. As per PLIC documentation, a hart context is a given > privilege mode on a given hart. Thus, cpu context ID & cpu numbers are not > same. Here is the PLIC register Maps in U54 core: > > Ref: https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf > > Memory address for Interrupt enable > Address > 0x0C00-2080 Hart 1 M-mode enables > 0x0C00 2094 End of Hart 1 M-mode enables > > 0x0C00-2100 Hart 1 S-mode enables > 0x0C00-2114 End of Hart 1 S-mode enables > > Memory map Claim/Threshold > Address > 0x0C20-1000 4B M-mode priority threshold > 0x0C20-1004 4B M-mode claim/complete > 0x0C20-2000 4B S-mode priority threshold > 0x0C20-2004 4B S-mode claim/complete > > The original PLIC patch was calculating based on handle->contextid which > will assume numbers on a HighFive Unleashed board as 2 4 6 8. > > In this patch, context id is assigned as cpu numbers which will be 1 2 3 4. > Thus it will lead to incorrect plic address access as shown below. Indeed. Can you try this branch, which puts back the OF contextid parsing from the original code: git://git.infradead.org/users/hch/riscv.git riscv-irq-simple.2 Gitweb: http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-irq-simple.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
