Hi Oleksij, > -----Original Message----- > From: Oleksij Rempel [mailto:o.rempel@xxxxxxxxxxxxxx] > Sent: Saturday, July 21, 2018 9:08 PM > To: Shawn Guo <shawnguo@xxxxxxxxxx>; Fabio Estevam > <fabio.estevam@xxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark > Rutland <mark.rutland@xxxxxxx>; A.s. Dong <aisheng.dong@xxxxxxx>; > Vladimir Zapolskiy <vladimir_zapolskiy@xxxxxxxxxx> > Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx>; devicetree@xxxxxxxxxxxxxxx; > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx> > Subject: [PATCH v5 1/4] dt-bindings: arm: fsl: add mu binding doc > > From: Dong Aisheng <aisheng.dong@xxxxxxx> > > The Messaging Unit module enables two processors within the SoC to > communicate and coordinate by passing messages (e.g. data, status and > control) through the MU interface. > > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > Cc: Sascha Hauer <kernel@xxxxxxxxxxxxxx> > Cc: Fabio Estevam <fabio.estevam@xxxxxxx> > Cc: Mark Rutland <mark.rutland@xxxxxxx> > Cc: devicetree@xxxxxxxxxxxxxxx > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: Dong Aisheng <aisheng.dong@xxxxxxx> Just let you know this patch also depends on another one which is already Acked by Rob. If you resend, would you please help pick that one in this series as well? [V4,1/5] dt-bindings: mailbox: allow mbox-cells to be equal to 0 https://patchwork.kernel.org/patch/10513197/ Regards Dong Aisheng > --- > .../devicetree/bindings/mailbox/fsl,mu.txt | 34 +++++++++++++++++++ > 1 file changed, 34 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/mailbox/fsl,mu.txt > > diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt > b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt > new file mode 100644 > index 000000000000..90e4905dfc69 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt > @@ -0,0 +1,34 @@ > +NXP i.MX Messaging Unit (MU) > +-------------------------------------------------------------------- > + > +The Messaging Unit module enables two processors within the SoC to > +communicate and coordinate by passing messages (e.g. data, status and > +control) through the MU interface. The MU also provides the ability for > +one processor to signal the other processor using interrupts. > + > +Because the MU manages the messaging between processors, the MU > uses > +different clocks (from each side of the different peripheral buses). > +Therefore, the MU must synchronize the accesses from one side to the > +other. The MU accomplishes synchronization using two sets of matching > +registers (Processor A-facing, Processor B-facing). > + > +Messaging Unit Device Node: > +============================= > + > +Required properties: > +------------------- > +- compatible : should be "fsl,<chip>-mu", the supported chips include > + imx8qxp, imx8qm. > +- reg : Should contain the registers location and length > +- interrupts : Interrupt number. The interrupt specifier format depends > + on the interrupt controller parent. > +- #mbox-cells: Must be 0. Number of cells in a mailbox > + > +Examples: > +-------- > +lsio_mu0: mailbox@5d1b0000 { > + compatible = "fsl,imx8qxp-mu"; > + reg = <0x0 0x5d1b0000 0x0 0x10000>; > + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <0>; > +}; > -- > 2.18.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
