On Fri, Jul 20, 2018 at 7:16 AM, Jacopo Mondi <jacopo@xxxxxxxxxx> wrote: > The 1.5 version of Engicam's i.Core MX6 CPU module features a different clock > provider for the ethernet's PHY interface. Adjust the FEC ptp clock to > reference CLK_ENET_REF clock source, and set SION bit of > MX6QDL_PAD_GPIO_16__ENET_REF_CLK to adjust the input path of that pin. > > The newly introduced imx6ql-icore-1.5.dtsi allows to collect in a single > place differences between version '1.0' and '1.5' of the module. > > Signed-off-by: Jacopo Mondi <jacopo@xxxxxxxxxx> Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
