The NAND driver looks for a clock named "core" and falls back to a pdev clock that has a wrong rate if not set. Signed-off-by: Daniel Mack <daniel@xxxxxxxxxx> --- arch/arm/boot/dts/pxa3xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi index 3851057bc77d..7f65791c0559 100644 --- a/arch/arm/boot/dts/pxa3xx.dtsi +++ b/arch/arm/boot/dts/pxa3xx.dtsi @@ -134,6 +134,7 @@ compatible = "marvell,pxa3xx-nand-controller"; reg = <0x43100000 90>; interrupts = <45>; + clock-names = "core"; clocks = <&clks CLK_NAND>; dmas = <&pdma 97 3>; dma-names = "data"; -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
