Hello!
On 05/29/2018 04:10 PM, Simon Horman wrote:
>> Define the Condor board dependent part of the I2C0 device node.
>>
>> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
>> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
>> the former chips now).
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
>>
>> ---
>> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
>> @@ -80,6 +80,28 @@
>> clock-frequency = <32768>;
>> };
>>
>> +&i2c0 {
>> + pinctrl-0 = <&i2c0_pins>;
>> + pinctrl-names = "default";
>> +
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + io_expander0: gpio@20 {
>
> Hi Sergei,
>
> I'm a little confused about where 0x20 and 0x21 are derived from.
> Could you explain a little?
r-carv3h_system_evaluation_board_rev020.pdf, pp. 16-17, lower left corners.
The schematics gives the 8-bit read/write addresses but we use uniform 7-bit
I2C address in DTs.
>> + compatible = "onnn,pca9654";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +
>> + io_expander1: gpio@21 {
>> + compatible = "onnn,pca9654";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> +};
>> +
>> &mmc0 {
>> pinctrl-0 = <&mmc_pins>;
>> pinctrl-1 = <&mmc_pins_uhs>;
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