On 26/04/2018 22:51:13+0200, Andrew Lunn wrote:
> > +
> > + mdio0: mdio@107009c {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "mscc,ocelot-miim";
> > + reg = <0x107009c 0x36>, <0x10700f0 0x8>;
> > + interrupts = <14>;
> > + status = "disabled";
> > +
> > + phy0: ethernet-phy@0 {
> > + reg = <0>;
> > + };
> > + phy1: ethernet-phy@1 {
> > + reg = <1>;
> > + };
> > + phy2: ethernet-phy@2 {
> > + reg = <2>;
> > + };
> > + phy3: ethernet-phy@3 {
> > + reg = <3>;
> > + };
>
> Hi Alexandre
>
> These are internal PHYs? Is there an option to use external PHYs for
> the ports which have internal PHYs?
>
> I'm just wondering if they should be linked together by default. Or a
> comment added to the commit message about why they are not linked
> together here.
>
They are dual media ports so they are not necessarily using the
integrated PHY but can use SerDEs1G lanes.
I'll add that to the commit message.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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