On Wed, Mar 28, 2018 at 8:47 PM, Manivannan Sadhasivam
<manivannan.sadhasivam@xxxxxxxxxx> wrote:
> Add gpio driver for Actions Semi OWL family S900 SoC. Set of registers
> controlling the gpio shares the same register range with pinctrl block.
>
> GPIO registers are organized as 6 banks and each bank controls the
> maximum of 32 gpios.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@xxxxxxxxx>
> +static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
> +{
> + u32 val;
> +
> + val = readl_relaxed(base);
> +
> + if (flag)
> + val |= BIT(pin);
> + else
> + val &= ~BIT(pin);
> +
> + writel_relaxed(val, base);
> +}
Hmm... Just realized that this driver misses locking.
Something like
owl_gpio_update_reg_locked()
{
spin_lock();
owl_gpio_update_reg();
spin_unlock();
}
> +
> +static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct owl_gpio *gpio = gpiochip_get_data(chip);
> +
> + /*
> + * GPIOs have higher priority over other modules, so either setting
> + * them as OUT or IN is sufficient
> + */
> + owl_gpio_update_reg(gpio->base + GPIO_OUTEN, offset, true);
...to use in such cases.
> +
> + return 0;
> +}
> +
> +static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct owl_gpio *gpio = gpiochip_get_data(chip);
> +
> + /* disable gpio output */
> + owl_gpio_update_reg(gpio->base + GPIO_OUTEN, offset, false);
> +
> + /* disable gpio input */
> + owl_gpio_update_reg(gpio->base + GPIO_INEN, offset, false);
...or
spin_lock();
owl_gpio_update_reg();
owl_gpio_update_reg();
spin_unlock();
...in this and similar cases.
> +}
--
With Best Regards,
Andy Shevchenko
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