On Fri, Mar 23, 2018 at 10:22:30PM +0100, Alexandre Belloni wrote:
> On 23/03/2018 at 14:17:48 -0700, Florian Fainelli wrote:
> > On 03/23/2018 01:11 PM, Alexandre Belloni wrote:
> > > +
> > > + phy0: ethernet-phy@0 {
> > > + reg = <0>;
> > > + };
> > > + phy1: ethernet-phy@1 {
> > > + reg = <1>;
> > > + };
> > > + phy2: ethernet-phy@2 {
> > > + reg = <2>;
> > > + };
> > > + phy3: ethernet-phy@3 {
> > > + reg = <3>;
> > > + };
> >
> > These PHYs should be defined at the board DTS level.
>
> Those are internal PHYs, present on the SoC, I doubt anyone will have
> anything different while using the same SoC.
With DSA, there is no need to list internal PHYs.
That is the trade off of having a standalone MDIO bus driver. Maybe
add a phandle to the internal MDIO bus? The switch driver could then
follow the phandle, and direct connect the internal PHYs?
Andrew
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