On Mon, Mar 19, 2018 at 5:31 AM, Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote: > On Sat, Mar 17, 2018 at 05:28:47PM +0800, Chen-Yu Tsai wrote: >> From: Icenowy Zheng <icenowy@xxxxxxx> >> >> There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in >> the syscon part, in the CCU of R40 SoC. >> >> Export a regmap of the CCU. >> >> Read access is not restricted to all registers, but only the GMAC >> register is allowed to be written. >> >> Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> >> Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> > > Gah, this is crazy. I'm really starting to regret letting that syscon > in in the first place... IMHO syscon is really a better fit. It's part of the glue layer and most other dwmac user platforms treat it as such and use a syscon. Plus the controls encompass delays (phase), inverters (polarity), and even signal routing. It's not really just a group of clock controls, like what we poorly modeled for A20/A31. I think that was really a mistake. As I mentioned in the cover letter, a slightly saner approach would be to let drivers add custom syscon entries, which would then require less custom plumbing. > And I'm not really looking forward the time where SCPI et al. will be > mature and we'll have the clock controller completely outside of our > control. I don't think it's going to happen for any of the older SoCs. The R40 only stands out because the GMAC controls are in the clock controller address space, presumably to be like the A20. ChenYu -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
