On 19/03/18 16:57, Stephen Boyd wrote:
[...]
+
+ if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
+ /* Enable Soft Stop/Start */
Sigh.
+ if (vbases[APC_BASE])
When is this false?
+ writel_relaxed(SSSCTL_VAL, vbases[APC_BASE] +
+ PWRCL_REG_OFFSET + SSSCTL_OFFSET);
+ /* Ensure SSSCTL config goes through before enabling ACD. */
+ mb();
Use writel instead.
Note that writel() only gives an implicit wmb() *before* the store to
ensure ordering against any previous writes. If this code really needs
to ensure that the given write has definitely completed before any other
accesses happen, then it still needs an explicit barrier *after* the
write*(), unless perhaps the next access is always guaranteed to be a
non-relaxed write (thus implicitly providing a suitable DSB).
Robin.
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