On Mon, Mar 19, 2018 at 10:14:19AM +0800, Chen-Yu Tsai wrote: > On Mon, Mar 19, 2018 at 3:07 AM, Mylène Josserand > <mylene.josserand@xxxxxxxxxxx> wrote: > > Hello Mark, > > > > Please, excuse me for this late answer and thank you for the review! > > > > On Wed, 7 Mar 2018 12:18:33 +0000 > > Marc Zyngier <marc.zyngier@xxxxxxx> wrote: > > > >> On 23/02/18 13:37, Mylène Josserand wrote: > >> > On Cortex-A7, the CNTVOFF register from arch timer is uninitialized. > >> > >> Only on A7? Is that specific to your platform? > > > > I do not really know other Allwinner's platforms about this subject. At > > least, the sun9i-a80 which is a Cortex-a15/a7 does not need that but it > > is necessary for sun8i-a83t which is a cortex-a7. Maybe, Chen-Yu or > > Maxime could help us on it. > > AFAIK all Allwinner CPUs need it if there isn't a firmware (PSCI) layer > beneath the kernel that will do the setup. We just have > "arm,cpu-registers-not-fw-configured" set for all the other SoCs that > have in-kernel SMP support, which includes the A31, A23, A33 and A80. Most of these ones are here for historical reasons though. Now that we have U-Boot properly setting it up, we could probably remove it. Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
