Hi ,
On Tue, Feb 20, 2018 at 2:10 PM, Shubhrajyoti Datta
<shubhrajyoti.datta@xxxxxxxxxx> wrote:
> Add reset bridge support. Once this bridge is enabled.
> The reset line(s) will be toggled. Generally it will be
> called after the bitstream load to reset the PL.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx>
> ---
> .../devicetree/bindings/fpga/xlnx,rst-bridge.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> new file mode 100644
> index 0000000..6f1bfc2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,rst-bridge.txt
> @@ -0,0 +1,22 @@
> +Xilinx fpga reset bridge
> +
> +The Xilinx reset bridge toggles the reset line to the PL
> +in Zynqmp Ultrascale plus.
> +
> +
> +Required properties:
> +- compatible : Should contain "xlnx,rst-bridge"
> +- reset : reset phandles
> +
> +Optional properties:
> +- bridge-enable : 0 if driver should disable bridge at startup
> + 1 if driver should enable bridge at startup
> + Default is to leave bridge in current state.
> +
> +See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
> +
> +Example:
> +fpga_rst_bridge: fpga_rst_bridge {
> + compatible = "xlnx,rst-bridge";
> + resets = <&rst 115>;
> +};
> --
> 2.1.1
>
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