From: Ondrej Jirman <megous@xxxxxxxxxx>
Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
Add support for it in the device tree.
Signed-off-by: Ondrej Jirman <megous@xxxxxxxxxx>
[Icenowy: Change to use r_ccu and change pinmux node name]
Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx>
Reviewed-by: Chen-Yu Tsai <wens@xxxxxxxx>
---
Changes in v2:
- Added Chen-Yu's Review tag.
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fc602aed60a6..57606900a949 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -716,6 +716,19 @@
status = "disabled";
};
+ r_i2c: i2c@1f02400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01f02400 0x400>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
+ clocks = <&r_ccu CLK_APB0_I2C>;
+ resets = <&r_ccu RST_APB0_I2C>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
--
2.15.1
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