On 06/02/14 16:46, Arnd Bergmann wrote: > On Wednesday 05 February 2014, srinivas kandagatla wrote: >> Currently l2cc bindings has few optional properties like. >> >> - arm,data-latency >> - arm,tag-latency >> - arm,dirty-latency >> - arm,filter-ranges >> - interrupts : >> - cache-id-part: >> - wt-override: >> >> These does not include properties to set "way-size", "associativity", >> "enabling prefetching", "Prefetch drop enable", "prefetch offset", >> "Double linefill" and few more in prefect control register and >> aux-control register. >> >> This is not just a issue with STi SOCs, having a quick look, I can see >> that few more SOCs have similar requirements to set these properties. >> >> We could do two things to get l2 setup automatically on STi SOCS. >> >> 1> Either define these properties case-by-case basic, which might be >> useful for other SOCs too. >> >> 2> Or Add new compatible string for STi SoCs so that they can >> automatically setup these values in cache-l2x0.c >> >> Am Ok with either approaches. >> > > I suggested 1 in the past, but the objection that I saw (can't > find the email at the moment) was that the additional settings > are "configuration" rather than "hardware properties". What I'd > really need to know from you is which of properties you listed > as missing above are actually needed for your platform, and whether > they can be classified as hardware specific or just configuration. On STi Platforms we need below properties to got for option 1. arm,way-size; arm,instruction-prefetch-enable; arm,data-prefetch-enable; we also want a property or a way to set "Shareable attribute Override Enable" bit in the Auxiliary Control Register, bit[22]. Thanks, srini > > Arnd > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
