On Friday 31 January 2014, srinivas kandagatla wrote: > > Sorry if I missed the initial review, but can you explain > > why this is needed to start with? > > On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set > the way-size explicit here. Unfortunately, we keep going back and forth on the L2 cache controller setup between "it should work automatically" and "we don't want to have configuration data in DT", where my personal opinion is that the first one is more important here. Now, there are a couple of properties that are defined in Documentation/devicetree/bindings/arm/l2cc.txt to let some of the things get set up automatically already. Can you check which bits are missing there, if any? Are they better described as "configuration" or "hardware" settings? Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
