On 12/13, Abhishek Sahu wrote: > - It has 2 instances of PCIE which uses AXI, AHB, AUX, SYS NOC > AXI and PIPE clocks. > - It has 2 instances of USB 3.0 which uses AUX, SLEEP, PIPE, > SYS NOC, mock UTMI and master clocks. > - It has 2 instances of SDCC which uses APSS and AHB clock. > SDCC1 requires ICE core clock also. > - All the PIPE clocks are external clocks which will be > registered in clock framework by PHY drivers. The enabling > and disabling of PIPE RCG clocks are dependent upon PHY > initialization sequence so BRANCH_HALT_DELAY flag is required for > these clocks. > > Signed-off-by: Abhishek Sahu <absahu@xxxxxxxxxxxxxx> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
