DRA72 uses USB3 PHY for the 2nd lane of PCIE. Add dt bindings property
to indicate if the USB3 PHY should be used for 2nd lane of PCIe.
Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index cd13e6157088..907a046e794b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -93,6 +93,8 @@ Optional properties:
register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
- syscon-pcs : phandle/offset pair. Phandle to the system control module and the
register offset to write the PCS delay value.
+ - "ti,configure-as-pcie" : property to indicate if the PHY should be
+ configured as PCIE PHY.
Deprecated properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
