On Thursday 30 January 2014, Patrice CHOTARD wrote: > From: Alexandre TORGUE <alexandre.torgue@xxxxxx> > > This patch adds support to STiD127 SoC. > The main adaptation is the L2 cache way size compare to STiH41x SoCs. > > Signed-off-by: alexandre torgue <alexandre.torgue@xxxxxx> > Signed-off-by: Patrice Chotard <patrice.chotard@xxxxxx> > --- > arch/arm/mach-sti/board-dt.c | 6 ++++++ > 1 file changed, 6 insertions(+) Wouldn't it be better to read this value from the l2 cache controller node? I'd assume there might be more SoCs that will need a similar change, so it's better to come up with a solution that doesn't involve changing the kernel every time. Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
