On 10/05, sean.wang@xxxxxxxxxxxx wrote: > From: Chen Zhong <chen.zhong@xxxxxxxxxxxx> > > Since the previous setup always sets the PLL using crystal 26MHz, this > doesn't always happen in every MediaTek platform. So the patch added > flexibility for assigning extra member for determining the PLL source > clock. > > Signed-off-by: Chen Zhong <chen.zhong@xxxxxxxxxxxx> > Signed-off-by: Sean Wang <sean.wang@xxxxxxxxxxxx> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
