On 28.09.2017 12:31, Vinod Koul wrote: > On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote: >> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels, >> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master >> modes. This driver is primarily supposed to be used by gpu/host1x in a >> master mode, performing 3D HW context stores. >> >> Dmitry Osipenko (5): >> clk: tegra: Add AHB DMA clock entry >> clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20 >> dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller >> dmaengine: Add driver for NVIDIA Tegra AHB DMA controller >> ARM: dts: tegra: Add AHB DMA controller nodes > > I don't think they are dependent, so consider sending them separately > Well, they are dependent in a sense of making driver usable. Only the "SCLK rate bump" patch isn't strictly needed. Splitting this series won't cause building failures, but all pieces should be in place for the working driver. So I suppose it is okay if clk patches would get in earlier than the others, I'll split the series. Thank you for the review. -- Dmitry -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
