When the arbitration between NOR and NAND flash is enabled the <FORCE_CSX> field bit[21] in the Data Flash Control Register needs to be set to 1 according to guidleine GL-5830741. Set the FORCE_CSX bit in NDCR for ARMADA370 variants as the arbitration is always enabled by default. Changes since v1: Thanks Miquel RAYNAL for the suggestion. * Deleted: "dt-bindings: mtd: pxa3xx: Add "marvell,nand-force-csx" compatible string" Not necessary to create a new compatible string. * "mtd-nand-pxa3xx-Set-FORCE_CSX-bit-to-ARMADA370-variants" Modified commit message. This commit sets the FORCE_CSX bit for all ARMADA370 variants. ---- Kalyan Kinthada (1): mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants. drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
