On 14.09.2017 10:16, Masahiro Yamada wrote:
Hi.
2017-09-14 17:04 GMT+09:00 Oleksij Rempel <ore@xxxxxxxxxxxxxx>:
Hi,
i assume arch/arm/boot/dts/socfpga.dtsi should be update as well. Right?
I think so.
(also arch/arm/boot/dts/socfpga_arria10.dtsi in the same way)
Hm.. according to
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf
Table 13-18: NAND Controller Module Data Space Address Range
Module Instance Start Address End Address
NAND_DATA 0xFF900000 0xFF9FFFFF
So <0xff900000 0x100000> seems to be a proper value.
The wrong property "dma-mask" was removed by
commit 60d920d32ca40660e382cf9ccbc236599a49e607.
On 14.09.2017 09:17, Masahiro Yamada wrote:
This example allocates too much for register regions. Especially,
there are only two registers in the "nand_data" interface of this
hardware (ADDR: 0x00, DATA: 0x10).
Signed-off-by: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx>
---
Documentation/devicetree/bindings/mtd/denali-nand.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt
b/Documentation/devicetree/bindings/mtd/denali-nand.txt
index 504291d..0ee8edb 100644
--- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
@@ -29,7 +29,7 @@ nand: nand@ff900000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "altr,socfpga-denali-nand";
- reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
+ reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 144 4>;
};
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