Add DT binding for eFuse controller available at Xilinx Zynq
SoC.
Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx>
Acked-by: Sören Brinkmann <soren.brinkmann@xxxxxxxxxx>
Acked-by: Rob Herring <robh@xxxxxxxxxx>
---
Changes in v2:
- Move doc to bindings/nvmem - suggested by Rob
- Add Rob's ACK
Documentation/devicetree/bindings/nvmem/zynq-efuse.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/zynq-efuse.txt
diff --git a/Documentation/devicetree/bindings/nvmem/zynq-efuse.txt b/Documentation/devicetree/bindings/nvmem/zynq-efuse.txt
new file mode 100644
index 000000000000..39817e9750c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/zynq-efuse.txt
@@ -0,0 +1,15 @@
+Device tree bindings for Zynq's eFuse Controller
+
+The Zynq eFuse controller provides the access to the chip efuses which contain
+information about device DNA, security settings and also device status.
+
+Required properties:
+ compatible: Compatibility string. Must be "xlnx,zynq-efuse".
+ reg: Specify the base and size of the EFUSE controller registers
+ in the memory map. E.g.: reg = <0xf800d000 0x20>;
+
+Example:
+efuse: efuse@f800d000 {
+ compatible = "xlnx,zynq-efuse";
+ reg = <0xf800d000 0x20>;
+};
--
1.9.1
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