The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
regions, clocks, resets, and optional vbus properties. These were
not described when the H3 compatible string was added.
Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys
found on the H3 SoC")
Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx>
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 005bc22938ff..893dd01dfe64 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -17,18 +17,21 @@ Required properties:
* "phy_ctrl"
* "pmu0" for H3, V3s and A64
* "pmu1"
- * "pmu2" for sun4i, sun6i or sun7i
+ * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3
+ * "pmu3" for sun8i-h3
- #phy-cells : from the generic phy bindings, must be 1
- clocks : phandle + clock specifier for the phy clocks
- clock-names :
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
* "usb0_phy", "usb1_phy" for sun8i
+ * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
- resets : a list of phandle + reset specifier pairs
- reset-names :
* "usb0_reset"
* "usb1_reset"
- * "usb2_reset" for sun4i, sun6i or sun7i
+ * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3
+ * "usb3_reset" for sun8i-h3
Optional properties:
- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
@@ -37,6 +40,7 @@ Optional properties:
- usb0_vbus-supply : regulator phandle for controller usb0 vbus
- usb1_vbus-supply : regulator phandle for controller usb1 vbus
- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+- usb3_vbus-supply : regulator phandle for controller usb3 vbus
Example:
usbphy: phy@0x01c13400 {
--
2.13.3
--
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