Add an mipi node, and also add mipi endpoints to vopb and vopl output port nodes. Signed-off-by: Jacob Chen <jacob-chen@xxxxxxxxxx> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 44 ++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b4ff50a..4965163 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1475,6 +1475,11 @@ #address-cells = <1>; #size-cells = <0>; + vopl_out_mipi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_in_vopl>; + }; + vopl_out_edp: endpoint@1 { reg = <1>; remote-endpoint = <&edp_in_vopl>; @@ -1516,6 +1521,11 @@ remote-endpoint = <&edp_in_vopb>; }; + vopb_out_mipi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_in_vopb>; + }; + }; }; @@ -1531,6 +1541,40 @@ status = "disabled"; }; + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x8000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>; + clock-names = "ref", "pclk", "phy_cfg"; + power-domains = <&power RK3399_PD_VIO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html