From: Bich Hemon <bich.hemon@xxxxxx>
This patch adds fifo mode support for rx and tx.
Signed-off-by: Gerald Baeza <gerald.baeza@xxxxxx>
---
drivers/tty/serial/stm32-usart.c | 3 +++
drivers/tty/serial/stm32-usart.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c
index 0338562..50948f6 100644
--- a/drivers/tty/serial/stm32-usart.c
+++ b/drivers/tty/serial/stm32-usart.c
@@ -453,6 +453,7 @@ static int stm32_startup(struct uart_port *port)
return ret;
val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
+ val |= USART_CR1_FIFOEN;
stm32_set_bits(port, ofs->cr1, val);
return 0;
@@ -467,6 +468,7 @@ static void stm32_shutdown(struct uart_port *port)
val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
val |= BIT(cfg->uart_enable_bit);
+ val |= USART_CR1_FIFOEN;
stm32_clr_bits(port, ofs->cr1, val);
free_irq(port->irq, port);
@@ -496,6 +498,7 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
cr1 |= BIT(cfg->uart_enable_bit);
+ cr1 |= USART_CR1_FIFOEN;
cr2 = 0;
cr3 = 0;
diff --git a/drivers/tty/serial/stm32-usart.h b/drivers/tty/serial/stm32-usart.h
index cd97ceb..9f0d0e8 100644
--- a/drivers/tty/serial/stm32-usart.h
+++ b/drivers/tty/serial/stm32-usart.h
@@ -134,6 +134,7 @@ struct stm32_usart_info stm32f7_info = {
#define USART_CR1_EOBIE BIT(27) /* F7 */
#define USART_CR1_M1 BIT(28) /* F7 */
#define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
+#define USART_CR1_FIFOEN BIT(29) /* H7 */
/* USART_CR2 */
#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */
--
1.9.1
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