On 06/08, Stefan Agner wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner <stefan@xxxxxxxx> > Tested-by: Fabio Estevam <fabio.estevam@xxxxxxx> > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
