On 12/06/17 10:36, Tony Lindgren wrote:
* Suman Anna <s-anna@xxxxxx> [170607 14:31]:
Hi Tony,
The following series configures the initial frequencies for the required
DPLLs and corresponding output divider clocks used by various remoteproc
accelerators (DSP, IVAHD) on OMAP4, OMAP5 & DRA7xx/AM57xx SoCs and the
GPU on DRA7xx/AM57xx SoCs. All these devices require Adaptive Voltage
Scaling (AVS) to be programmed at all OPPs at boot time, which is
programmed in the bootloader. Furthermore, DVFS is not supported on
these domains implying a one-time OPP clock frequency setup.
Tero, care to comment or ack this series?
These have been in use in TI releases for quite a while already, and
look fine, thus:
Acked-by: Tero Kristo <t-kristo@xxxxxx>
(Didn't quite think my ack was needed for them so didn't respond
earlier, sorry.)
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
