On Thu, Jun 08, 2017 at 02:10:23PM +0200, Thomas Petazzoni wrote: > Hello, > > On Wed, 7 Jun 2017 17:24:20 -0500, Rob Herring wrote: > > On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote: > > > This commit adds the Device Tree binding documentation for the Marvell > > > GICP, an extension to the GIC that allows to trigger GIC SPI interrupts > > > using memory transactions. It is used by the ICU unit in the Marvell > > > CP110 block to turn wired interrupts inside the CP into SPI interrupts > > > at the GIC level in the AP. > > > > Sounds like an MSI block? > > Marc Zyngier answered on this (much better than I could have done). > > > > +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available > > > + for this GICP > > > > These are base+size? > > Correct. Does your question suggest that I should update the binding > document to make this explicit? Yes, please. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
