CPU2 has its own power domain PD_CPU2, and CPU3 has PD_CPU3.
Signed-off-by: Andreas Färber <afaerber@xxxxxxx>
---
v4: new (split off due to dt-bindings dependency)
arch/arm/boot/dts/s500.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
index 51a48741d4c0..4e4478a3ec08 100644
--- a/arch/arm/boot/dts/s500.dtsi
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -7,6 +7,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/s500-powergate.h>
/ {
compatible = "actions,s500";
@@ -43,6 +44,7 @@
compatible = "arm,cortex-a9";
reg = <0x2>;
enable-method = "actions,s500-smp";
+ power-domains = <&sps S500_PD_CPU2>;
};
cpu3: cpu@3 {
@@ -50,6 +52,7 @@
compatible = "arm,cortex-a9";
reg = <0x3>;
enable-method = "actions,s500-smp";
+ power-domains = <&sps S500_PD_CPU3>;
};
};
--
2.12.3
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