Hi Stephen, Michael,
On Fri, 2017-03-03 at 15:50 -0800, Stephen Boyd wrote:
> On 03/03, Vlad Zakharov wrote:
> >
> > Hi Michael, Stephen,
> >
> > On Tue, 2017-02-21 at 16:11 +0300, Vlad Zakharov wrote:
> > >
> > > AXS10X boards manages it's clocks using various PLLs. These PLL has same
> > > dividers and corresponding control registers mapped to different addresses.
> > > So we add one common driver for such PLLs.
> > >
> > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and
> > > ODIV. Output clock value is managed using these dividers.
> > >
> > > We add pre-defined tables with supported rate values and appropriate
> > > configurations of IDIV, FBDIV and ODIV for each value.
> > >
> > > As of today we add support for PLLs that generate clock for the
> > > following devices:
> > > * ARC core on AXC CPU tiles.
> > > * ARC PGU on ARC SDP Mainboard.
> > > and more to come later.
> > >
> > > Acked-by: Rob Herring <robh@xxxxxxxxxx>
> > > Signed-off-by: Vlad Zakharov <vzakhar@xxxxxxxxxxxx>
> > > Signed-off-by: Jose Abreu <joabreu@xxxxxxxxxxxx>
> > > Cc: Michael Turquette <mturquette@xxxxxxxxxxxx>
> > > Cc: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> > > Cc: Mark Rutland <mark.rutland@xxxxxxx>
> >
> > Maybe you have any comments or remarks about this patch? And if you don't could you please apply it.
> >
>
> I haven't reviewed it yet. The merge window is upon us right now
> so I'll probably get to going through the queue this weekend/next
> week.
>
Please treat this message as a polite reminder to review my patch.
It is required for some subsystems on our boards, e.g. for ARC PGU.
Thanks.
--
Best regards,
Vlad Zakharov <vzakhar@xxxxxxxxxxxx>��.n��������+%������w��{.n����z�{��ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f
