On 03/09/2017 04:37 PM, Bjorn Andersson wrote:
On Thu 09 Mar 10:07 CET 2017, Vivek Gautam wrote: [..]+ phy@34000 { + compatible = "qcom,msm8996-qmp-pcie-phy"; + reg = <0x034000 0x488>;Drop the leading 0 from the address.
Okay, will drop it.
+ #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>; + clock-names = "aux", "cfg_ahb", "ref"; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + resets = <&gcc GCC_PCIE_PHY_BCR>, + <&gcc GCC_PCIE_PHY_COM_BCR>, + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; + reset-names = "phy", "common", "cfg"; + + pciephy_0: lane@0 {The "@xyz" part should match the first value in "reg", i.e. 35000 here.
Right, i think this came from my older version of patches. Will correct it. Regards Vivek
+ reg = <0x035000 0x130>, + <0x035200 0x200>, + <0x035400 0x1dc>; + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "lane0"; + }; + + pciephy_1: lane@1 { + ... + ... + };Regards, Bjorn
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