The dual Cortex-A9 MPCore inside socfpga has a standard PMU unit for
each core mapped in the DAP memory space. Add support for it!
Tested with perf on a Cyclone 5 SoC DK.
Reported-by: Alberto Dassatti <alberto.dassatti@xxxxxxxxxx>
Signed-off-by: Florian Vaussard <florian.vaussard@xxxxxxxxxx>
Tested-by: Alberto Dassatti <alberto.dassatti@xxxxxxxxxx>
---
arch/arm/boot/dts/socfpga.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 478047e..a892de9 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -52,6 +52,15 @@
};
};
+ pmu: pmu@ff111000 {
+ compatible = "arm,cortex-a9-pmu";
+ interrupt-parent = <&intc>;
+ interrupts = <0 176 4>, <0 177 4>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ reg = <0xff111000 0x1000>,
+ <0xff113000 0x1000>;
+ };
+
intc: intc@fffed000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
--
2.7.4
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