On 02/22/2017 05:19 AM, Jonas Gorski wrote: > Add documentation for the bindings of the high speed SPI controller found > on newer bcm63xx SoCs. > > Signed-off-by: Jonas Gorski <jonas.gorski@xxxxxxxxx> > --- > .../devicetree/bindings/spi/spi-bcm63xx-hsspi.txt | 35 ++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt > > diff --git a/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt b/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt > new file mode 100644 > index 000000000000..3b0a2220b896 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/spi-bcm63xx-hsspi.txt > @@ -0,0 +1,35 @@ > +Binding for Broadcom BCM6328 SPI controller > + > +Required properties: > +- compatible: must contain of "brcm,bcm6328-hsspi". > +- reg: Base address and size of the controllers memory area. > +- interrupts: Interrupt for the SPI block. > +- clocks: phandle of the SPI clock. > +- clock-names: must be "hsspi". > +- #address-cells: <1>, as required by generic SPI binding. > +- #size-cells: <0>, also as required by generic SPI binding. > + > +Optional properties: > +- num-cs: some controllers have less than 8 cs signals. Defaults to 8 > + if absent. > +- clocks: a second handle for the PLL clock. > +- clock-names: must be named "pll", if present. I have not found chips where the PLL may be optional, but there may be ways to have the same PLL and UBUS clocks feeding into the HSSPI block. Reviewed-by: Florian Fainelli <f.fainelli@xxxxxxxxx> -- Florian -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
