On 23.2.2017 10:28, Anatolij Gustschin wrote:
> On Wed, 22 Feb 2017 16:04:47 +0100
> Michal Simek michal.simek@xxxxxxxxxx wrote:
> ...
>>> + /* program latency */
>>> + usleep_range(prog_latency_1000us, prog_latency_1000us + 500);
>>
>> Based on my colleague for spartan6 this should be 5ms and other xilinx
>> fpgas can take up to 7.5ms.
>>
>> In general, it is better to poll for INIT_B pin==High (but that takes
>> another GPIO) and wait until at least 10 ms before timeout.
>
> checked in the ug380.pdf, it depends on the speed grade, for some
> spartan6 it can be max. 4ms, for others 5ms. It is a max. value,
> INIT_B can go high earlier, but in my hw setup INIT_B is not
> connected. Someone with a hw setup with INIT_B connected can
> add optional support for INIT_P polling.
>
> ...
>>> +static int xilinx_spi_write_complete(struct fpga_manager *mgr,
>>> + struct fpga_image_info *info)
>>> +{
>>> + struct xilinx_spi_conf *conf = mgr->priv;
>>> + int wait;
>>> +
>>> + if (gpiod_get_value(conf->done))
>>> + return 0;
>>> +
>>> + wait = info->config_complete_timeout_us / FPGA_MIN_CFG_WAIT_US;
>>> + if (info->config_complete_timeout_us % FPGA_MIN_CFG_WAIT_US)
>>> + wait += 1;
>>> +
>>> + while (wait--) {
>>> + usleep_range(FPGA_MIN_CFG_WAIT_US, FPGA_MIN_CFG_WAIT_US + 5);
>>> +
>>> + if (gpiod_get_value(conf->done))
>>> + return 0;
>>> + }
>>> +
>>
>> Based on my colleague:
>> IMHO, for step 4 it is better to do these steps to cover more possible
>> configuration DONE scenarios:
>>
>> While ((DONE==0) and (NOT TIMEOUT)) {
>> Continue to apply CCLK cycles;
>> Check DONE;
>> timeout++;
>> }
>>
>> Apply at least 8 more CCLK cycles.
>>
>> The timeout should be equivalent to at least 10 ms of time.
>
> You mead Step 8 I think, not step 4. Will see what I can change.
This was just c&p from his reply with different steps numbers. :-)
Thanks,
Michal
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