> -----Original Message----- > From: Scott Wood [mailto:oss@xxxxxxxxxxxx] > Sent: Thursday, February 16, 2017 2:37 AM > To: Y.T. Tang <yuantian.tang@xxxxxxx>; mturquette@xxxxxxxxxxxx > Cc: sboyd@xxxxxxxxxxxxxx; robh+dt@xxxxxxxxxx; mark.rutland@xxxxxxx; > linux-clk@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; linux- > kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Subject: Re: [PATCH 2/2] clk: qoriq: Separate root input clock for core PLLs on > ls1012a > > On Wed, 2017-02-15 at 13:47 +0800, yuantian.tang@xxxxxxx wrote: > > From: Tang Yuantian <Yuantian.Tang@xxxxxxx> > > > > ls1012a has separate input root clocks for core PLLs versus the > > platform PLL, with the latter described as sysclk in the hw docs. > > If a second input clock, named "coreclk", is present, this clock will > > be used for the core PLLs. > > > > Signed-off-by: Scott Wood <oss@xxxxxxxxxxxx> > > Signed-off-by: Tang Yuantian <yuantian.tang@xxxxxxx> > > --- > > drivers/clk/clk-qoriq.c | 91 > > +++++++++++++++++++++++++++++++++++++++++----- > > Why did you reset the author on these patches? Have you changed anything? > Why aren't they marked either v2 or resend? > I should have marked as v2 or resend. If anything changed, I take it over and dropped the 2/3 patch in your original patch set to speed up the merge, which I think so. This patch set blocks other patches and 20 days passed, no any action on it. We can't account on you to push it. That's why I take it over and resend it. All in all, what you suggest to do to make them get accepted ASAP? Regards, Yuantian > -Scott ��.n��������+%������w��{.n����z�{��ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f
