On Fri, Feb 10, 2017 at 07:16:10PM +0200, Michael S. Tsirkin wrote: > On Thu, Feb 09, 2017 at 06:31:18PM +0000, Will Deacon wrote: > > On ARM (and other archs such as > > Power), having a mismatch between a cacheable and a non-cacheable mapping > > can result in a loss of coherency between the two (for example, if the > > non-cacheable gues accesses bypass the cache, but the cacheable host > > accesses allocate in the cache). > > I guess it's an optimization to avoid cache snoops for non-cacheable accesses? The architecture doesn't rationalise the decision, but a micro-architecture could indeed implement the optimisation you suggest (and we do observe the loss of coherency in practice). Will -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
