Hi R-Car GEN3 PCIe modules have 32-bit connect to internal AXI bus. Could please somebody with lowlevel hardware knowledge answer, if this is PCIe module limitation, or internal bus limitation. Depending on that, different modification of renesas/r8a779[56].dtsi files is needed: either - wrap only pcie nodes into 32-bit sub-node of /soc, or - turn entire /soc subtree to 32-bit. Problem I'm trying to solve is related to DMA ranges handling. Architecture code needs explicit information on DMA range limitations caused by interconnect. See [1] thread for details. Nikita [1] https://www.mail-archive.com/linux-renesas-soc@xxxxxxxxxxxxxxx/msg10449.html -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
