On Mon, Nov 28, 2016 at 05:04:26PM -0600, Grygorii Strashko wrote: > The TS_COMP output in the CPSW CPTS module is asserted for > ts_comp_length[15:0] RCLK periods when the time_stamp value compares > with the ts_comp_val[31:0] and the length value is non-zero. The > TS_COMP pulse edge occurs three RCLK periods after the values > compare. A timestamp compare event is pushed into the event FIFO when > TS_COMP is asserted. > > This patch adds support of Pulse-Per-Second (PPS) by using the > timestamp compare output. The CPTS driver adds one second of counter > value to the ts_comp_val register after each assertion of the TS_COMP > output. The TS_COMP pulse polarity and width are configurable in DT. I really dislike this patch. You go through contortions to get from the timecounter back to the raw HW counter. That is rather ugly. Can you adjust the frequency of the keystone devices in hardware? If so, then please implement it, and just disable PPS for the CPSW. The only reason I used the timecounter for frequency adjustment was because the am335x HW is broken. But this shouldn't hold back other newer HW without the same silicon flaws. Thanks, Richard -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
