On Thu, Nov 17, 2016 at 7:06 AM, Andrew Jeffery <andrew@xxxxxxxx> wrote: > +* Device tree bindings for the Aspeed LPC Controller We are going overboard with the lingo sometimes, to the point that we do not understand how terse things become. LPC = Low Pin Count, right? Explain that right here: it is a slow external bus, right? > +The Aspeed LPC controller contains registers for a variety of functions. Not > +all registers for a function are contiguous, and some registers are referenced > +by functions outside the LPC controller. > + > +Note that this is separate from the H8S/2168 compatible register set occupying > +the start of the LPC controller address space. > + > +Some significant functions in the LPC controller: > + > +* LPC Host Controller > +* Host Interface Controller Host interface to what? > +* iBT Controller What is iBT? > +* SuperIO Scratch registers Again more context please. With standards documents, either explain everything or provide pointers for the information. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
