On Mon, Oct 31, 2016 at 04:55:24PM +0200, Georgi Djakov wrote: > Add support for the PLL, which generates the higher range of CPU > frequencies on MSM8916 platforms. > > Signed-off-by: Georgi Djakov <georgi.djakov@xxxxxxxxxx> > --- > .../devicetree/bindings/clock/qcom,a53pll.txt | 20 +++++ > drivers/clk/qcom/Kconfig | 9 +++ > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/a53-pll.c | 94 ++++++++++++++++++++++ > 4 files changed, 124 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt > create mode 100644 drivers/clk/qcom/a53-pll.c > > diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt > new file mode 100644 > index 000000000000..6a8c03bfbcb5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt > @@ -0,0 +1,20 @@ > +MSM8916 A53 PLL Binding > +--------------- > +The A53 PLL on MSM8916 platforms is the main CPU PLL used for frequencies > +above 1GHz. > + > +Required properties : > +- compatible : Shall contain only one of the following: > + > + "qcom,a53pll-msm8916" Generally, the ordering is <vendor>,<soc>-<block>. > + > +- reg : shall contain base register location and length > +- #clock-cells : must be set to <0> > + > +Example: > + > + a53pll: a53pll@b016000 { clock@... > + compatible = "qcom,a53pll-msm8916"; > + reg = <0x0b016000 0x40>; > + #clock-cells = <0>; > + }; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html