On Tue, 2016-11-08 at 11:49 +0000, Mark Rutland wrote: > > My understanding of ISA (which may be flawed) is that it's not part of > the PCI host bridge, but rather on x86 it happens to share the IO space > with PCI. Sort-of. On some systems it actually goes through PCI and there's a PCI->ISA bridge that uses substractive decoding to the legacy devices. > So, how about this becomes: > > Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which > provides access to some legacy ISA devices. > > I believe that we could theoretically have multiple independent LPC/ISA > busses, as is possible with PCI on !x86 systems. If the current ISA code > assumes a singleton bus, I think that's something that needs to be fixed > up more generically. > > I don't see why we should need any architecture-specific code here. Why > can we not fix up the ISA bus code in drivers/of/address.c such that it > handles multiple ISA bus instances, and translates all sub-device > addresses relative to the specific bus instance? What in that code prevents that today ? Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
