On Wed, Sep 28, 2016 at 12:20:16AM +0930, Andrew Jeffery wrote: > The SPI1 function was associated with the wrong pins: The functions that > those pins provide is either an SPI debug or passthrough function > coupled to SPI1. Make the SPI1 mux function configure the relevant pins > and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins > that were already defined. > > The notation used in the datasheet's multi-function pin table for the SoC is > often creative: in this case the SYS* signals are enabled by a single bit, > which is nothing unusual on its own, but in this case the bit was also > participating in a multi-bit bitfield and therefore represented multiple > functions. This fact was overlooked in the original patch. > > Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver) > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx> > --- > Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 4 +- Acked-by: Rob Herring <robh@xxxxxxxxxx> > drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 86 ++++++- > 2 files changed, 81 insertions(+), 9 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
