On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh.xie@xxxxxxxxx wrote:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0x0>;
> + clocks = <&clockgen 1 0>;
> + next-level-cache = <&l2>;
> + cpu-idle-states = <&CPU_PH20>;
> + };
[...]
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_PH20: cpu-ph20 {
> + compatible = "arm,idle-state";
> + idle-state-name = "PH20";
> + arm,psci-suspend-param = <0x00010000>;
> + entry-latency-us = <1000>;
> + exit-latency-us = <1000>;
> + min-residency-us = <3000>;
> + };
> + };
There's no PSCI node in this file, and none from am included file, so
this doesn't look right.
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>,
> + <&cpu1>,
> + <&cpu2>,
> + <&cpu3>;
> + };
The compatible string should be "arm,cortex-a72-pmu".
Thanks,
Mark.
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