On 07/12/2016 12:17 AM, Michael Turquette wrote: > Quoting Sylwester Nawrocki (2016-07-11 03:33:42) >> On 07/08/2016 06:17 PM, Michael Turquette wrote: > Sure, but it's only a few lines of code to this, and there are examples > in the kernel already. > >> Additionally, the "There is half-multiplier before the SPI" comment >> seems to be obfuscating how the hardware really looks like to me. >> It talks about multiplier (which reminds me of PLLs with a divider >> in the feedback loop) while there is a simple divider which should >> be considered as an integral part of the controller IP block. >> >> While we are at it, I'd propose to change this comment to something >> like: >> >> /* The SCLK_SPI clock is divided internally by 2 */ > > It's your choice, but debug output would benefit from showing the real > clock frequency at some point. OK, it's indeed fairly easy to add a fixed rate divide-by-two clock, but for the older SoCs we would need to also model the internal mux, gate, and an 8-bit divider. Then it becomes a bit bigger task. Anyway it might be worth to try it, this could let us deprecate the samsung,spi-src-clk property and for all the SoCs use assigned-clock-parents. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
