On 07/11/2016 02:14 PM, Philipp Zabel wrote:
Am Montag, den 11.07.2016, 14:02 +0530 schrieb Archit Taneja:
[...]
+ /* PXL PLL setup */
+ if (tc->test_pattern) {
I couldn't find out who is setting tc->test_pattern. Is it always
0?
Hm, you are right. I wonder what a good mechanism would be to enable a
test pattern for a bridge driver. Module parameters? We don't have
anyhting like V4L2_CID_TEST_PATTERN in drm. I could also drop test
pattern support from the initial patch and submit it separately.
Module parameter sounds like a good option.
Ok.
Although, it seems like the pll is enabled only when test_pattern is
set. How does the bridge work if the pll isn't enabled?
The PXL PLL is only necessary regenerate the pixel clock from the DSI HS
clock, or to create the test pattern. In DPI mode the pixel clock from
the parallel interface is used directly.
Okay. Thanks for the clarification.
Archit
regards
Philipp
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