The i.MX 7 series currently consists of two SoCs: i.MX 7Solo and 7Dual. The i.MX 7Solo implements a subset of features available on i.MX 7Dual, hence create imx7s.dtsi as the base device tree. The i.MX 7Dual's additional features over i.MX 7Solo are: - Second Cortex-A7 core - Second Gigabit Ethernet controller - EPD (Electronc Paper Display, not yet part of the device tree) - PCIe (not yet part of the device tree) - Additional USB2.0 OTG controller Signed-off-by: Stefan Agner <stefan@xxxxxxxx> --- arch/arm/boot/dts/imx7d.dtsi | 923 +++---------------------------------------- arch/arm/boot/dts/imx7s.dtsi | 880 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 928 insertions(+), 875 deletions(-) create mode 100644 arch/arm/boot/dts/imx7s.dtsi diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 6b3faa2..51c13cb 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Toradex AG * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -40,54 +41,10 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/clock/imx7d-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include "imx7d-pinfunc.h" -#include "skeleton.dtsi" +#include "imx7s.dtsi" / { - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; - i2c3 = &i2c4; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX7D_CLK_ARM>; - }; - cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; @@ -95,221 +52,6 @@ }; }; - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x31001000 0x1000>, - <0x31002000 0x1000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - - ckil: clock-cki { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; - - osc: clock-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-parent = <&intc>; - }; - - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; - }; - }; - }; - - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; - }; - }; - - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; - }; - }; - - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; - }; - }; - }; - }; - - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&hugo_funnel_out_port0>; - }; - }; - - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; - }; - }; - }; - }; - - funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&ca_funnel_out_port0>; - }; - }; - - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - slave-mode; /* M4 input */ - }; - }; - - port@2 { - reg = <0>; - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - }; - - funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; - ca_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - ca_funnel_in_port1: endpoint { - slave-mode; - remote-endpoint = <&etm1_out_port>; - }; - }; - - /* funnel output port */ - port@2 { - reg = <0>; - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - - /* the other input ports are not connect to anything */ - }; - }; - - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; - }; - }; - etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; @@ -330,626 +72,57 @@ }; }; }; +}; - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - aips1: aips-bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30000000 0x400000>; - ranges; - - gpio1: gpio@30200000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30200000 0x10000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@30210000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30210000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@30220000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30220000 0x10000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@30230000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30230000 0x10000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@30240000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30240000 0x10000>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@30250000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30250000 0x10000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@30260000 { - compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; - reg = <0x30260000 0x10000>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - wdog1: wdog@30280000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30280000 0x10000>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; - }; - - wdog2: wdog@30290000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x30290000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; - status = "disabled"; - }; - - wdog3: wdog@302a0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302a0000 0x10000>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; - status = "disabled"; - }; - - wdog4: wdog@302b0000 { - compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; - reg = <0x302b0000 0x10000>; - interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; - status = "disabled"; - }; - - iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - }; - - gpt1: gpt@302d0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302d0000 0x10000>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; - }; - - gpt2: gpt@302e0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302e0000 0x10000>; - interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt3: gpt@302f0000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x302f0000 0x10000>; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - gpt4: gpt@30300000 { - compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; - reg = <0x30300000 0x10000>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - }; - - gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; - reg = <0x30340000 0x10000>; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clks IMX7D_CLK_DUMMY>; - status = "disabled"; - }; - - anatop: anatop@30360000 { - compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", - "syscon", "simple-bus"; - reg = <0x30360000 0x10000>; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - - reg_1p0d: regulator-vdd1p0d@210 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd1p0d"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1200000>; - anatop-reg-offset = <0x210>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <8>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1200000>; - anatop-enable-bit = <31>; - }; - }; - - snvs: snvs@30370000 { - compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; - reg = <0x30370000 0x10000>; - - snvs_rtc: snvs-rtc-lp { - compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap = <&snvs>; - offset = <0x34>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - }; - - snvs_poweroff: snvs-poweroff { - compatible = "syscon-poweroff"; - regmap = <&snvs>; - offset = <0x38>; - mask = <0x60>; - }; - - snvs_pwrkey: snvs-powerkey { - compatible = "fsl,sec-v4.0-pwrkey"; - regmap = <&snvs>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - linux,keycode = <KEY_POWER>; - wakeup-source; - }; - }; - - clks: ccm@30380000 { - compatible = "fsl,imx7d-ccm"; - reg = <0x30380000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>; - clock-names = "ckil", "osc"; - }; - - src: src@30390000 { - compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; - reg = <0x30390000 0x10000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - #reset-cells = <1>; - }; - }; - - aips2: aips-bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30400000 0x400000>; - ranges; - - adc1: adc@30610000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30610000 0x10000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - status = "disabled"; - }; - - adc2: adc@30620000 { - compatible = "fsl,imx7d-adc"; - reg = <0x30620000 0x10000>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ADC_ROOT_CLK>; - clock-names = "adc"; - status = "disabled"; - }; - - pwm1: pwm@30660000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30660000 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PWM1_ROOT_CLK>, - <&clks IMX7D_PWM1_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm2: pwm@30670000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30670000 0x10000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PWM2_ROOT_CLK>, - <&clks IMX7D_PWM2_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm3: pwm@30680000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30680000 0x10000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PWM3_ROOT_CLK>, - <&clks IMX7D_PWM3_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - pwm4: pwm@30690000 { - compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; - reg = <0x30690000 0x10000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PWM4_ROOT_CLK>, - <&clks IMX7D_PWM4_ROOT_CLK>; - clock-names = "ipg", "per"; - #pwm-cells = <2>; - status = "disabled"; - }; - - lcdif: lcdif@30730000 { - compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; - reg = <0x30730000 0x10000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; - status = "disabled"; - }; - }; - - aips3: aips-bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30800000 0x400000>; - ranges; - - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - flexcan1: can@30a00000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a00000 0x10000>; - interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - flexcan2: can@30a10000 { - compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; - reg = <0x30a10000 0x10000>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CAN2_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - i2c1: i2c@30a20000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a20000 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_I2C1_ROOT_CLK>; - status = "disabled"; - }; - - i2c2: i2c@30a30000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a30000 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_I2C2_ROOT_CLK>; - status = "disabled"; - }; - - i2c3: i2c@30a40000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a40000 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_I2C3_ROOT_CLK>; - status = "disabled"; - }; - - i2c4: i2c@30a50000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; - reg = <0x30a50000 0x10000>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_I2C4_ROOT_CLK>; - status = "disabled"; - }; - - uart4: serial@30a60000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a60000 0x10000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART4_ROOT_CLK>, - <&clks IMX7D_UART4_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart5: serial@30a70000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a70000 0x10000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART5_ROOT_CLK>, - <&clks IMX7D_UART5_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart6: serial@30a80000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a80000 0x10000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART6_ROOT_CLK>, - <&clks IMX7D_UART6_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart7: serial@30a90000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30a90000 0x10000>; - interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART7_ROOT_CLK>, - <&clks IMX7D_UART7_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - usbotg1: usb@30b10000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b10000 0x200>; - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbotg2: usb@30b20000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b20000 0x200>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbh: usb@30b30000 { - compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x30b30000 0x200>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_USB_CTRL_CLK>; - fsl,usbphy = <&usbphynop3>; - fsl,usbmisc = <&usbmisc3 0>; - phy_type = "hsic"; - dr_mode = "host"; - phy-clkgate-delay-us = <400>; - status = "disabled"; - }; - - usbmisc1: usbmisc@30b10200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b10200 0x200>; - }; - - usbmisc2: usbmisc@30b20200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b20200 0x200>; - }; - - usbmisc3: usbmisc@30b30200 { - #index-cells = <1>; - compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; - reg = <0x30b30200 0x200>; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY1_CLK>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - }; - - usbphynop3: usbphynop3 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; - clock-names = "main_clk"; - }; - - usdhc1: usdhc@30b40000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b40000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC1_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; +&aips3 { + usbotg2: usb@30b20000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b20000 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; - usdhc2: usdhc@30b50000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b50000 0x10000>; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC2_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; + usbmisc2: usbmisc@30b20200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b20200 0x200>; + }; - usdhc3: usdhc@30b60000 { - compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; - reg = <0x30b60000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_USDHC3_ROOT_CLK>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - status = "disabled"; - }; + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + }; - fec1: ethernet@30be0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30be0000 0x10000>; - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; + fec2: ethernet@30bf0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30bf0000 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; +}; - fec2: ethernet@30bf0000 { - compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; - reg = <0x30bf0000 0x10000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - status = "disabled"; - }; +&ca_funnel_ports { + port@1 { + reg = <1>; + ca_funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; }; }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi new file mode 100644 index 0000000..a5fd2d7 --- /dev/null +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -0,0 +1,880 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2016 Toradex AG + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/imx7d-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX7D_CLK_ARM>; + }; + }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x1000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; + + ckil: clock-cki { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&intc>; + }; + + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etr_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; + }; + }; + }; + + funnel@30083000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + slave-mode; /* M4 input */ + }; + }; + + port@2 { + reg = <0>; + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + funnel@30041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ca_funnel_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* funnel output port */ + port@2 { + reg = <0>; + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + + /* the other input ports are not connect to anything */ + }; + }; + + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + aips1: aips-bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog1: wdog@30280000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30280000 0x10000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; + }; + + wdog2: wdog@30290000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x30290000 0x10000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; + status = "disabled"; + }; + + wdog3: wdog@302a0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302a0000 0x10000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; + status = "disabled"; + }; + + wdog4: wdog@302b0000 { + compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; + reg = <0x302b0000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; + status = "disabled"; + }; + + iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + gpt1: gpt@302d0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT1_ROOT_CLK>; + clock-names = "ipg", "per"; + }; + + gpt2: gpt@302e0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt3: gpt@302f0000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + gpt4: gpt@30300000 { + compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; + reg = <0x30300000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_GPT4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + + gpr: iomuxc-gpr@30340000 { + compatible = "fsl,imx7d-iomuxc-gpr", "syscon"; + reg = <0x30340000 0x10000>; + }; + + ocotp: ocotp-ctrl@30350000 { + compatible = "syscon"; + reg = <0x30350000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>; + status = "disabled"; + }; + + anatop: anatop@30360000 { + compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x30360000 0x10000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + + reg_1p0d: regulator-vdd1p0d@210 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p0d"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + anatop-reg-offset = <0x210>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <8>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1200000>; + anatop-enable-bit = <31>; + }; + }; + + snvs: snvs@30370000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x30370000 0x10000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x60>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + }; + + clks: ccm@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; + + src: src@30390000 { + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; + reg = <0x30390000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + }; + + aips2: aips-bus@30400000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30400000 0x400000>; + ranges; + + adc1: adc@30610000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30610000 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + status = "disabled"; + }; + + adc2: adc@30620000 { + compatible = "fsl,imx7d-adc"; + reg = <0x30620000 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ADC_ROOT_CLK>; + clock-names = "adc"; + status = "disabled"; + }; + + pwm1: pwm@30660000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30660000 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM1_ROOT_CLK>, + <&clks IMX7D_PWM1_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@30670000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30670000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM2_ROOT_CLK>, + <&clks IMX7D_PWM2_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@30680000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30680000 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM3_ROOT_CLK>, + <&clks IMX7D_PWM3_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@30690000 { + compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; + reg = <0x30690000 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PWM4_ROOT_CLK>, + <&clks IMX7D_PWM4_ROOT_CLK>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + + lcdif: lcdif@30730000 { + compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; + reg = <0x30730000 0x10000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + }; + + aips3: aips-bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan1: can@30a00000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a00000 0x10000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + flexcan2: can@30a10000 { + compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; + reg = <0x30a10000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CAN2_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C1_ROOT_CLK>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C2_ROOT_CLK>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C3_ROOT_CLK>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_I2C4_ROOT_CLK>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART4_ROOT_CLK>, + <&clks IMX7D_UART4_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART5_ROOT_CLK>, + <&clks IMX7D_UART5_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART6_ROOT_CLK>, + <&clks IMX7D_UART6_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART7_ROOT_CLK>, + <&clks IMX7D_UART7_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + usbotg1: usb@30b10000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b10000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbh: usb@30b30000 { + compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x30b30000 0x200>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_USB_CTRL_CLK>; + fsl,usbphy = <&usbphynop3>; + fsl,usbmisc = <&usbmisc3 0>; + phy_type = "hsic"; + dr_mode = "host"; + phy-clkgate-delay-us = <400>; + status = "disabled"; + }; + + usbmisc1: usbmisc@30b10200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b10200 0x200>; + }; + + usbmisc3: usbmisc@30b30200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x30b30200 0x200>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY1_CLK>; + clock-names = "main_clk"; + }; + + usbphynop3: usbphynop3 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; + clock-names = "main_clk"; + }; + + usdhc1: usdhc@30b40000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b40000 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC1_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@30b50000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b50000 0x10000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC2_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@30b60000 { + compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; + reg = <0x30b60000 0x10000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_USDHC3_ROOT_CLK>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + fec1: ethernet@30be0000 { + compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; + reg = <0x30be0000 0x10000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, + <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + status = "disabled"; + }; + }; + }; +}; -- 2.8.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html